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features ? single 2.5v - 3.6v or 2.7v - 3.6v supply ? rapids serial interface: 66 mhz maximum clock frequency ? spi compatible modes 0 and 3 ? user configurable page size ? 512 bytes per page ? 528 bytes per page ? page size can be factory pre-configured for 512 bytes ? page program operation ? intelligent programming operation ? 8,192 pages (512/528 bytes/page) main memory ? flexible erase options ? page erase (512 bytes) ? block erase (4 kbytes) ? sector erase (64 kbytes) ? chip erase (32 mbits) ? two sram data buffers (512/528 bytes) ? allows receiving of data whil e reprogramming the flash array ? continuous read capability through entire array ? ideal for code shadowing applications ? low-power dissipation ? 7 ma active read current typical ? 25 a standby current typical ? 15 a deep power down typical ? hardware and software data protection features ? individual sector ? sector lockdown for secure code and data storage ? individual sector ? security: 128-byte security register ? 64-byte user programmable space ? unique 64-byte device identifier ? jedec standard manufacturer and device id read ? 100,000 program/erase cycles per page minimum ? data retention ? 20 years ? industrial temperature range ? green (pb/halide-free/rohs co mpliant) packaging options 1. description the at45db321d is a 2.5-volt or 2.7-vol t, serial-interface sequential access flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. the at45db321d supports rapids serial interface for applications requiring very high speed operat ions. rapids serial interface is spi com- patible for frequencies up to 66 mhz. its 34,603,008 bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. in addition to the main memory, the at45db321d also contains two sram buffers of 512/528 bytes each. the buffers allow the receiving of data while a page in the main memory is being reprogrammed, as well as writing a continuous data stream. eeprom emulation (bit or byte alterabil- ity) is easily handled with a self-contained three step read-modify-write operation. unlike conventional flash memories that are accessed randomly with multiple address lines and a parallel interface, the dataflash uses a rapids serial interface to 32-megabit 2.5-volt or 2.7-volt dataflash ? at45db321d 3597o?dflash?10/09
2 3597o?dflash?10/09 at45db321d sequentially access its data. the simple sequent ial access dramatically reduces active pin count, facilitates hardware layout, increases syst em reliability, minimizes switching noise, and reduces package size. the device is optimized fo r use in many commercial and industrial appli- cations where high-density, low-pin count, low-voltage and low-po wer are essential. to allow for simple in-system reprogrammabi lity, the at45db321d does not require high input voltages for programming. the device operates from a single power supply, 2.7v to 3.6v, for both the program and read operations. the at45db321d is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of the serial input (si), serial output (so), and the serial clock (sck). all programming and erase cycles are self-timed. 2. pin configurations and pinouts figure 2-1. mlf (1) (vdfn) top view note: 1. the metal pad on the bottom of the mlf package is floating. this pad can be a ?no connect? or connected to gnd. figure 2-2. soic top view figure 2-3. bga package ball-out (top view) figure 2-4. tsop top view: type 1 note: tsop package is not recommended for new designs. future die shrinks will support 8-pin packages only. s i s ck re s et c s s o gnd vcc wp 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5 si sck reset cs so gnd vcc wp a b c d e 5 4 3 2 1 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vcc gnd sck cs rdy/bsy wp si so reset 1 2 3 4 5 6 8 9 10 11 12 13 14 28 2 26 25 24 23 22 21 20 19 18 1 16 15 rdy/busy reset wp nc nc vcc gnd nc nc nc cs sck si so nc nc nc nc nc nc nc nc nc nc nc nc nc nc
3 3597o?dflash?10/09 at45db321d table 2-1. pin configurations symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in t he standby mode (not deep power-down mode), and the output pin (so) will be in a high-impedanc e state. when the device is deselected, data will not be accepted on the input pin (si). a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an operation. when e nding an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin is always latched on the rising edge of sck, while output data on the so pin is always clocked out on the falling edge of sck. ? input si serial input: the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched on the rising edge of sck. ? input so serial output: the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. ? output wp write protect: when the wp pin is asserted, all sectors specified for protection by the sector protection register will be protected against prog ram and erase operations regardless of whether the enable sector protection command has been issued or not. the wp pin functions independently of the software contro lled protection method. after the wp pin goes low, the content of the sector protection register cannot be modified. if a program or erase command is issued to the device while the wp pin is asserted, the device will simply ignore the command and perform no operat ion. the device will return to the idle state once the cs pin has been deasserted. the enable sector protection command and sector lockdown command, however, will be recognized by the device when the wp pin is asserted. the wp pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input reset reset: a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on rese t circuit, so there are no restrictions on the reset pin during power-on sequences. if this pin and feature are not utilized it is recommended that the reset pin be driven high externally. low input rdy/busy ready/busy: this open drain output pin will be driven low when the device is busy in an internally self-timed operation. this pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during prog ramming/erase operations, compare operations, and page-to-buffer transfers. the busy status indicates that the flash memo ry array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. ? output v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious re sults and should not be attempted. ?power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ? ground
4 3597o?dflash?10/09 at45db321d 3. block diagram 4. memory array to provide optimal flexibility, the memory array of the at45db321d is divided into three levels of granularity comprising of sectors, blocks, and pages. the ?memory architecture diagram? illustrates the breakdown of each level and details the number of pages per sector and block. all program operations to the dataflash occur on a page by page basis. the erase operations can be performed at the chip, sector, block or page level. figure 4-1. memory architecture diagram flash memory array page (512/528 bytes) buffer 2 (512/528 bytes) buffer 1 (512/528 bytes) i/o interface sck cs reset vcc gnd rdy/busy wp so si s ector 0a = 8 pa g e s 4,096/4,224 byte s s ector 0b = 120 pa g e s 61,440/6 3 , 3 60 byte s block = 4,096/4,224 byte s 8 pa g e s s ector 0a s ector 0b pa g e = 512/52 8 byte s page 0 page 1 page 6 page 7 page 8 page 9 page 8 ,190 page 8 ,191 block 0 page 14 page 15 page 16 page 17 page 1 8 block 1 s ector architecture block architecture page architecture block 0 block 1 block 62 block 6 3 block 64 block 65 block 1,022 block 1,02 3 block 126 block 127 block 12 8 block 129 s ector 1 s ector 6 3 = 12 8 pa g e s 65,5 3 6/67,5 8 6 byte s block 2 s ector 1 = 12 8 pa g e s 65,5 3 6/67,5 8 4 byte s s ector 62 = 12 8 pa g e s 65,5 3 6/67,5 8 4 byte s s ector 2 = 12 8 pa g e s 65,5 3 6/67,5 8 4 byte s
5 3597o?dflash?10/09 at45db321d 5. device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in table 15-1 on page 28 through table 15-7 on page 31 . a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, tog- gling the sck pin controls the loading of t he opcode and the desired buffer or main memory address location through the si (serial input) pin. all instructions, addresses, and data are trans- ferred with the most significant bit (msb) first. buffer addressing for the dataflash standard page size (528 bytes) is referenced in the datasheet using the terminology bfa9 - bfa0 to denote the 10 address bits required to desig- nate a byte address within a buffer. main memory addressing is referenced using the terminology pa12 - pa0 and ba9 - ba0, where pa12 - pa0 denotes the 13 address bits required to designate a page address and ba9 - ba0 denotes the 10 address bits required to designate a byte address within the page. for ?power of 2? binary page size (512 bytes) the buffer addressing is referenced in the datasheet using the conventional terminology bfa8 - bfa0 to denote the 9 address bits required to designate a byte address within a buffer. main memory addressing is referenced using the terminology a21 - a0, where a21 - a9 denotes the 13 address bits required to desig- nate a page address and a8 - a0 denotes the 9 address bits required to designate a byte address within a page. 6. read commands by specifying the appropriate opcode, data can be read from the main memory or from either one of the two sram data buffers. the dataflas h supports rapids protocols for mode 0 and mode 3. please refer to the ?detailed bit-level read timing? diagrams in this datasheet for details on the clock cycle sequences for each mode. 6.1 continuous array read (legacy co mmand: e8h): up to 66 mhz by supplying an initial starting address for the main memory array, the continuous array read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. the dataflash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. to perform a cont inuous read from the dataflash standard page size (528 bytes), an opcode of e8h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and 4 don?t care bytes. the first 13 bits (pa12 - pa0) of the 23-bit addres s sequence specify which page of the main mem- ory array to read, and the last 10 bits (ba9 - ba0) of the 23-bit address sequence specify the starting byte address within the page. to perform a continuous read from the binary page size (512 bytes), the opcode (e8h) must be clocked into the device followed by three address bytes and 4 don?t care bytes. the first 13 bits (a21 - a9) of the 22-bits sequence specify which page of the main memory array to read, and the last 9 bits (a8 - a0) of the 22-bits address sequence specify the starting byte address within the page. the don?t care bytes that follow the address bytes are needed to initialize the read operation. following the don?t care bytes, additional clock pulses on the sck pin will result in data be ing output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main memory is reached during a
6 3597o?dflash?10/09 at45db321d continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading ba ck at the beginning of the firs t page of memory. as with cross- ing over page boundaries, no de lays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-stat e the output pin (so). the maximum sck frequency allowable for the continuous array read is defined by the f car1 specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.2 continuous array read (high frequ ency mode: 0bh): up to 66 mhz this command can be used with the serial interface to read the main memory array sequentially in high speed mode for any clock frequency up to the maximum specified by f car1 . to perform a continuous read array with the page size set to 528 bytes, the cs must first be asserted then an opcode 0bh must be clocked into the device followed by three address bytes and a dummy byte. the first 13 bits (pa12 - pa0) of the 23-bit address sequence specify which page of the main memory array to read, and the last 10 bits (ba9 - ba0) of the 23-bit address sequence specify the starting byte address within the page. to perform a continuous read with the page size set to 512 bytes, the opcode, 0bh, must be clocked into the device followed by three address bytes (a21 - a0) and a dummy byte. follo wing the dummy byte, additional clock pulses on the sck pin will result in data bei ng output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, and the read- ing of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the be ginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will con- tinue reading back at the beginning of the fi rst page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to -high transition on the cs pin will term inate the r ead operation and tri-state the output pin (so). the maxi mum sck frequency allowable for the continuous array read is defined by the f car1 specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.3 continuous array read (low frequen cy mode: 03h): up to 33 mhz this command can be used with the serial interface to read the main memory array sequentially without a dummy byte up to maximum frequencies specified by f car2 . to perform a continuous read array with the page size set to 528 bytes, the cs must first be asserted then an opcode, 03h, must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence). the first 13 bits (pa12 - pa0) of the 23-bit address sequence specify which page of the main memory array to read, and the last 10 bits (ba9 - ba0) of the 23-bit address sequence specify the starting byte address within the page. to perform a contin- uous read with the page size set to 512 bytes, the opcode, 03h, must be clocked into the device followed by three address bytes (a21 - a0). follo wing the address bytes, additional clock pulses on the sck pin will result in data bei ng output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, and the read- ing of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the be ginning of the next page with no delays incurred
7 3597o?dflash?10/09 at45db321d during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will con- tinue reading back at the beginning of the fi rst page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to -high transition on the cs pin will term inate the r ead operation and tri-state the output pin (so). the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.4 main memory page read a main memory page read allows the user to read data directly from any one of the 8,192 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. to start a page read from the dataflash standard page size (528 bytes), an opcode of d2h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and 4 don?t care bytes. the first 13 bits (pa12 - pa0) of the 23-bit address sequence specify the page in main memory to be read, and the last 10 bits (ba9 - ba0) of the 23-bit address sequence specify the starting byte address within that page. to start a page read from the binary page size (512 bytes), the opcode d2h must be clocked into the device followed by three address bytes and 4 don?t care bytes. the first 13 bits (a21 - a9) of the 22-bits sequence specify which page of the main memory array to read, and the last 9 bits (a8 - a0) of the 22-bits address sequence specify the starting byte address within the page. the don?t care bytes that follow the address bytes are sent to initialize the read opera- tion. following the don?t care bytes, additional pulses on sck result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main memory is reached, the device will c ontinue reading back at the beginning of the same page. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the main memory page read is defined by the f sck specification. the main memory page read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.5 buffer read the sram data buffers can be accessed independe ntly from the main me mory array, and utiliz- ing the buffer read command allows data to be sequentially read directly from the buffers. four opcodes, d4h or d1h for buffer 1 and d6h or d3h for buffer 2 can be used for the buffer read command. the use of each opc ode depends on the maximum sck frequen cy that will be used to read data from the buffer. the d4h and d6h opcode can be used at any sck frequency up to the maximum specified by f car1 . the d1h and d3h opcode can be used for lower frequency read operations up to the maximum specified by f car2 . to perform a buffer read from the dataflash standard buffer (528 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 14 don?t care bits and 10 buffer address bits (bfa9 - bfa0). to perform a buffer read from the binary buffer (512 bytes), the opcode must be clocked into the device followed by three address bytes com- prised of 15 don?t care bits and 9 buffer addr ess bits (bfa8 - bfa0). following the address bytes, one don?t care byte must be clocked in to initialize the read operation. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care byte, and the reading of data . when the end of a buffer is reached, the device will c ontinue reading back at the beginning of the buffer. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so).
8 3597o?dflash?10/09 at45db321d 7. program and erase commands 7.1 buffer write data can be clocked in from the input pin (si) into either buffer 1 or buffer 2. to load data into the dataflash standard buffer (528 bytes), a 1-byte opcode, 84h for buffer 1 or 87h for buffer 2, must be clocked into the device, followed by thre e address bytes comprised of 14 don?t care bits and 10 buffer address bits (bfa9 - bfa0). the 10 buffer address bits specify the first byte in the buffer to be written. to load data into the binary buffers (512 bytes each), a 1-byte opcode 84h for buffer 1 or 87h for buffer 2, must be clocked into the device, followed by three address bytes comprised of 15 don?t care bits and 9 buffer address bits (bfa8 - bfa0). the 9 buffer address bits specify the first byte in the buffer to be written. after the last address byte has been clocked into the device, data can then be clocked in on s ubsequent clock cycles. if the end of the data buffer is reached, the device will wrap around back to the beginni ng of the buffer. data will con- tinue to be loaded into the buffer until a low-to-high transition is detected on the cs pin. 7.2 buffer to main memory page program with built-in erase data written into either buffer 1 or buffer 2 can be programmed into the main memory. a 1-byte opcode, 83h for buffer 1 or 86h for buffer 2, must be clocked into the device. for the dataflash standard page size (528 bytes), the opcode must be followed by three address bytes consist of 1 don?t care bit, 13 page address bits (pa12 - pa0) that specify the page in the main memory to be written and 10 don?t care bits. to perform a buffer to main memory page program with built-in erase for the binary page size (512 bytes), the opcode 83h for buffer 1 or 86h for buffer 2, must be clocked into the device followed by three address bytes consisting of 2 don?t care bits 13-page address bits (a21 - a9) that specify the page in the main memory to be written and 9 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into the specified page in main memory. both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 7.3 buffer to main memory page program without built-in erase a previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. a 1-byte opcode, 88h for buffer 1 or 89h for buffer 2, must be clocked into the device. for the dataflash standard page size (528 bytes), the opcode must be followed by three address bytes consist of 1 don?t care bit, 13 page address bits (pa12 - pa0) that specify the page in the main memory to be written and 10 don?t care bits. to perform a buffer to main memory page program without built-in erase for the binary page size (512 bytes), the opcode 88h for buffer 1 or 89h for buffer 2, must be clocked into the device followed by three address bytes consisting of 2 don?t care bits, 13 page address bits (a21 - a9) that specify the page in the main memory to be written and 9 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will program the data stored in the buffer into the specified page in the main mem- ory. it is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (page erase or block erase). the programming of the page is internally self-timed and should take place in a maximum time of t p . during this time, the status register and the rdy/busy pin will indicate that the part is busy.
9 3597o?dflash?10/09 at45db321d 7.4 page erase the page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program to be utilized at a later time. to perform a page erase in the dataflash standard page size (528 bytes), an opcode of 81h must be loaded into the device, followed by three address bytes comprised of 1 don?t care bit, 13 page address bits (pa12 - pa0) that specify the page in the main memory to be erased and 10 don?t care bits. to perform a page erase in the binary page size (512 bytes), the opcode 81h must be loaded into the device, followed by three address bytes co nsist of 2 don?t care bits, 13 page address bits (a21 - a9) that specify the page in the main memory to be erased and 9 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will erase the selected page (the erased state is a logical 1). the erase operation is internally self-timed and should take place in a maxi- mum time of t pe . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 7.5 block erase a block of eight pages can be erased at one time. this command is useful when large amounts of data has to be written into the device. th is will avoid using mult iple page erase commands. to perform a block erase for the dataflash standard page size (528 bytes), an opcode of 50h must be loaded into the device, followed by three address bytes comprised of 1 don?t care bit, 10 page address bits (pa12 -pa3) and 13 don?t care bits. the 10 page address bits are used to specify which block of eight pages is to be eras ed. to perform a block erase for the binary page size (512 bytes), the opcode 50h must be loaded into the device, followed by three address bytes consisting of 2 don?t care bits, 10 page address bits (a21 - a12) and 12 don?t care bits. the 10 page address bits are used to specify wh ich block of eight pages is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected block of eight pages. the erase operation is internally self-timed and should take place in a maximum time of t be . during this time, the status register and the rdy/busy pin will indicate that the part is busy. table 7-1. block erase addressing pa12 / a21 pa11 / a20 pa10/ a19 pa9/ a18 pa8/ a17 pa 7 / a16 pa6 / a15 pa5/ a14 pa4/ a13 pa3/ a12 pa2 / a11 pa1 / a10 pa0/ a9 block 0000000000xxx 0 0000000001xxx 1 0000000010xxx 2 0000000011xxx 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1111111100xxx1020 1111111101xxx1021 1111111110xxx1022 1111111111xxx1023
10 3597o?dflash?10/09 at45db321d 7.6 sector erase the sector erase command can be used to individually erase any sector in the main memory. there are 64 sectors and only one sector can be erased at one time. to perform sector 0a or sector 0b erase for the dataflash standard page si ze (528 bytes), an opcode of 7ch must be loaded into the device, followed by three address bytes comprised of 1 don?t care bit, 10 page address bits (pa12 - pa3) and 13 don?t care bi ts. to perform a sector 1-63 erase, the opcode 7ch must be loaded into the device, followed by three address bytes comprised of 1 don?t care bit, 6 page address bits (pa12 - pa7) and 17 don?t care bits. to perform sector 0a or sector 0b erase for the binary page size (512 bytes), an opcode of 7ch must be loaded into the device, followed by three address bytes compris ed of 2 don?t care bit and 10 page address bits (a21 - a12) and 12 don?t care bits. to perform a sector 1-63 erase, the opcode 7ch must be loaded into the device, followed by three addres s bytes comprised of 2 don?t care bits and 6 page address bits (a21 - a16) and 16 don?t care bits. the page address bits are used to spec- ify any valid address location within the sector which is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the sele cted sector. the erase operation is internally self-timed and should take place in a maximum time of t se . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 7.7 chip erase (1) the entire main memory can be erased at one time by using the chip erase command. to execute the chip erase command, a 4-byte command sequence c7h, 94h, 80h and 9ah must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. after the last bit of the opcode sequence has been clocked in, the cs pin can be deas- serted to start the erase process. the erase operation is internally self-timed and should take place in a time of t ce . during this time, the status register will indicate that the device is busy. the chip erase command w ill not affect sectors that are prot ected or locked down; the contents of those sectors will re main unchanged. only those sectors that are not prot ected or locked down will be erased. note: 1. refer to the errata regarding chip erase on page 56 . table 7-2. sector erase addressing pa12/ a21 pa11/ a20 pa1 0/ a19 pa9/ a18 pa 8/ a17 pa7 / a16 pa6/ a15 pa5/ a14 pa4/ a13 pa 3 / a12 pa2 / a11 pa1/ a10 pa0/ a9 sector 0000000000xxx 0a 0000000001xxx 0b 000001 xxxxxxx 1 000010 xxxxxxx 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 111100 xxxxxxx 60 111101 xxxxxxx 61 111110 xxxxxxx 62 111111 xxxxxxx 63
11 3597o?dflash?10/09 at45db321d the wp pin can be asserted while the device is eras ing, but protection will not be activated until the internal erase cycle completes. figure 7-1. chip erase note: 1. refer to the errata regarding chip erase on page 56 . 7.8 main memory page program through buffer this operation is a combination of the buffer write and buffer to main memory page program with built-in erase operations. data is first clocked into buffer 1 or buffer 2 from the input pin (si) and then programmed into a specified page in the main memory. to perform a main memory page program through buffer for the dataflash standard page size (528 bytes), a 1-byte opcode, 82h for buffer 1 or 85h for buffer 2, must first be clocked into the device, followed by three address bytes. the address bytes are compris ed of 1 don?t care bit, 13 page address bits, (pa12 - pa0) that select the page in the main memory where data is to be written, and 10 buffer address bits (bfa9 - bfa0) that select the first byte in the buffer to be written. to perform a main memory page program through buffer for the binary page size (512 bytes), the opcode 82h for buffer 1 or 85h for buffer 2, must be clocke d into the device followed by three address bytes consisting of 2 don?t care bits, 13 page address bits (a21 - a9) that specify the page in the main memory to be written, and 9 buffer address bits (bfa8 - bfa0) that selects the first byte in the buffer to be written. after all address bytes are clocked in, the part will take data from the input pins and store it in the specified data buffer. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transition on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 8. sector protection two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. the software controlled method relies on the use of software commands to enable and disable sector protection while the hardware con- trolled method employs the use of the write protect (wp ) pin. the selection of which sectors that are to be protected or unprotected against program and erase operations is specified in the nonvolatile sector protection register. the status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the status register. command byte 1 byte 2 byte 3 byte 4 chip erase c7h 94h 80h 9ah opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 c s e a ch tr a n s ition repre s ent s 8 b it s s i
12 3597o?dflash?10/09 at45db321d 8.1 software sector protection 8.1.1 enable sector protection command sectors specified for protection in the sector protection register can be protected from program and erase operations by issuing the enable sector protection command. to enable the sector protection using the software controlled method, the cs pin must first be asserted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte command sequence must be clocked in via the input pin (si). after the last bit of the command sequence has been clocked in, the cs pin must be deasserted after which the sector protection will be enabled. figure 8-1. enable sector protection 8.1.2 disable sector protection command to disable the sector protection using the software controlled method, the cs pin must first be asserted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte sequence for the disable sector protection command must be clocked in via the input pin (si). after the last bit of the command sequence has been clocked in, the cs pin must be deasserted after wh ich the sector protection will be disabled. the wp pin must be in the deasserted state; otherwise, the disable sector protec tion command will be ignored. figure 8-2. disable sector protection 8.1.3 various aspects about software controlled protection software controlled protection is useful in applications in which the wp pin is not or cannot be controlled by a host processor. in such instances, the wp pin may be left floating (the wp pin is internally pulled high) and sector protection can be controlled using the enable sector protection and disable sector protection commands. if the device is power cycled, then the software controlled protection will be disabled. once the device is powered up, the enable sector protecti on command should be reissued if sector pro- tection is desired and if the wp pin is not used. command byte 1 byte 2 byte 3 byte 4 enable sector protection 3dh 2ah 7fh a9h opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si command byte 1 byte 2 byte 3 byte 4 disable sector protection 3dh 2ah 7fh 9ah opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si
13 3597o?dflash?10/09 at45db321d 9. hardware controlled protection sectors specified for protection in the sector protection register and the sector protection reg- ister itself can be protected from program and erase operations by asserting the wp pin and keeping the pin in its asserted state. the sector protection register and any sector specified for protection cannot be erased or reprogrammed as long as the wp pin is asserted. in order to modify the sector protection register, the wp pin must be deasserted. if the wp pin is perma- nently connected to gnd, then the content of the sector protection register cannot be changed. if the wp pin is deasserted, or permanently connected to v cc , then the content of the sector protection register can be modified. the wp pin will override the software controlled protection method but only for protecting the sectors. for example, if the sectors were not previously protected by the enable sector protec- tion command, then simply asserting the wp pin would enable the sector protection within the maximum specified t wpe time. when the wp pin is deasserted; however, the sector protection would no longer be enabled (after the maximum specified t wpd time) as long as the enable sec- tor protection command was not issued while the wp pin was asserted. if the enable sector protection command was issued before or while the wp pin was asserted, then simply deassert- ing the wp pin would not disable the sector protec tion. in this case, the disable sector protection command would need to be issued while the wp pin is deasserted to disable the sec- tor protection. the disable sector protecti on command is also ignored whenever the wp pin is asserted. a noise filter is incorporated to help protect against spurious noise that may inadvertently assert or deassert the wp pin. the table below details the sector protection status for various scenarios of the wp pin, the enable sector protection command, and the disable sector protection command. figure 9-1. wp pin and protection status wp 12 3 table 9-1. wp pin and protection status time period wp pin enable sector protection command disable sector protection command sector protection status sector protection register 1high command not issued previously ? issue command x issue command ? disabled disabled enabled read/write read/write read/write 2 low x x enabled read only 3high command issued during period 1 or 2 ? issue command not issued yet issue command ? enabled disabled enabled read/write read/write read/write
14 3597o?dflash?10/09 at45db321d 9.1 sector protection register the nonvolatile sector protection register specifies which sectors are to be protected or unpro- tected with either the software or hardware controlled protection methods. the sector protection register contains 64 bytes of data, of which byte locations 0 through 63 contain values that specify whether sectors 0 through 63 will be protected or unprotected. the sector protection register is user modifiable and must first be erased before it can be reprogrammed. table 9-3 illustrates the format of the sector protection register.: note: 1. the default value for bytes 0 through 63 when shipped from atmel is 00h. x = don?t care. table 9-2. sector protection register sector number 0 (0a, 0b) 1 to 63 protected see table 9-3 ffh unprotected 00h table 9-3. sector 0 (0a, 0b) 0a 0b bit 3, 2 data value (pages 0-7) (pages 8-127) bit 7, 6 bit 5, 4 bit 1, 0 sectors 0a, 0b unprotected 00 00 xx xx 0xh protect sector 0a (pages 0-7) 11 00 xx xx cxh protect sector 0b (pages 8-127) 00 11 xx xx 3xh protect sectors 0a (pages 0-7), 0b (pages 8-127) (1) 11 11 xx xx fxh
15 3597o?dflash?10/09 at45db321d 9.1.1 erase sector protection register command in order to modify and change the values of the sector protection register, it must first be erased using the erase sector protection register command. to erase the sector protection register, the cs pin must first be asserted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device via the si pin. the 4-byte opcode sequence must start with 3dh and be followed by 2ah, 7fh, and cfh. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initiate the internally self-timed erase cycle. the erasing of the sector protection re gister should take place in a time of t pe , during which time the status register will indicate that the device is busy. if the device is powered- down before the completion of the erase cycle, then the contents of the sector protection regis- ter cannot be guaranteed. the sector protection register can be erased with the sector protection enabled or disabled. since the erased state (ffh) of each byte in the sector protection register is used to indicate that a sector is specified for protection, leaving the sector protection enabled during the erasing of the register allows the protection scheme to be more effective in the prevention of accidental programming or erasing of the device. if for some reason an erroneous program or erase com- mand is sent to the device imm ediately after erasing the sector protection register and before the register can be reprogramm ed, then the erroneous progra m or erase command will not be processed because all sectors would be protected. figure 9-2. erase sector protection register 9.1.2 program sector protection register command once the sector protection register has been erased, it can be reprogrammed using the pro- gram sector protection register command. to program the sector protection register, the cs pin must first be asserted and the appropri- ate 4-byte opcode sequence must be clocked into the device via the si pin. the 4-byte opcode sequence must start with 3dh and be followed by 2ah, 7fh, and fch. after the last bit of the opcode sequence has been clocked into the device, the data for the contents of the sector pro- tection register must be clocked in. as described in section 9.1 , the sector protection register contains 64 bytes of data, so 64 bytes must be clocked into the device. the first byte of data cor- responds to sector 0, the second byte corresponds to sector 1, and so on with the last byte of data corresponding to sector 63. command byte 1 byte 2 byte 3 byte 4 erase sector protection register 3dh 2ah 7fh cfh opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si
16 3597o?dflash?10/09 at45db321d after the last data byte has been clocked in, the cs pin must be deasserted to initiate the inter- nally self-timed program cycle. the programming of the sector protection register should take place in a time of t p , during which time the stat us register will indicate that the device is busy. if the device is powered-down during the program cycle, then the contents of the sector protection register cannot be guaranteed. if the proper number of data bytes is not clocked in before the cs pin is deasserted, then the protection status of the sectors corresponding to the bytes not clocked in can not be guaranteed. for example, if only the first two bytes are clocked in instead of the complete 62 bytes, then the protection status of the last 62 sectors cannot be guaranteed. furthermore, if more than 64 bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. for instance, if 65 bytes of data are clocked in, t hen the 65th byte will be stored at byte location 0 of the sector protection register. if a value other than 00h or ffh is clocked into a byte location of the sector protection register, then the protection status of the sector corresponding to that byte location cannot be guaran- teed. for example, if a value of 17h is clocked into byte location 2 of the sector protection register, then the protection status of sector 2 cannot be guaranteed. the sector protection register can be reprogrammed while the sector protection enabled or dis- abled. being able to reprogram the sector protection register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than dis- abling sector protection completely. the program sector protection register command utilizes the internal sram buffer 1 for pro- cessing. therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. figure 9-3. program sector protection register command byte 1 byte 2 byte 3 byte 4 program sector protection register 3dh 2ah 7fh fch d a t a byte n opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 d a t a byte n + 1 d a t a byte n + 6 3 c s e a ch tr a n s ition repre s ent s 8 b it s s i
17 3597o?dflash?10/09 at45db321d 9.1.3 read sector protection register command to read the sector protection register, the cs pin must first be asserted. once the cs pin has been asserted, an opcode of 32h and 3 dummy bytes must be clocked in via the si pin. after the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the sck pins will result in data for the content of the sect or protection register being output on the so pin. the first byte corresponds to sector 0 ( 0a, 0b), the second byte corresponds to sector 1 and the last byte (byte 64) corresponds to sector 63. once the last byte of the sector protection register has been clo cked out, any additional clock pulses will result in unde fined data being output on the so pin. the cs must be deasserted to terminate the read sector protection reg- ister operation and put the output into a high-impedance state. note: xx = dummy byte figure 9-4. read sector protection register 9.1.4 various aspects about the sector protection register the sector protection register is subject to a limit of 10,000 erase/program cycles. users are encouraged to carefully evaluate the number of times the sector protection register will be modified during the course of the applications? life cycle. if the application requires that the sec- tor protection register be modified more than the specified limit of 10,000 cycles because the application needs to temporarily unprotect individual sectors (sector protection remains enabled while the sector protection regi ster is reprogrammed), then the application will need to limit this practice. instead, a combination of temporarily unprotecting individual sectors along with dis- abling sector protection completely will need to be implement ed by the applicatio n to ensure that the limit of 10,000 cycles is not exceeded. command byte 1 byte 2 byte 3 byte 4 read sector protecti on register 32h xxh xxh xxh opcode x x x d a t a byte n d a t a byte n + 1 c s d a t a byte n + 6 3 s i s o e a ch tr a n s ition repre s ent s 8 b it s
18 3597o?dflash?10/09 at45db321d 10. security features 10.1 sector lockdown the device incorporates a sector lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read only. this is useful for applications that require the ability to permanently protect a nu mber of sectors against malicious attempts at altering program code or security information. once a sector is locked down, it can never be erased or pro- grammed, and it can never be unlocked. to issue the sector lockdown command, the cs pin must first be asserted as it would be for any other command. once the cs pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. the 4-byte opcode sequence must start with 3dh and be followed by 2ah, 7fh, and 30h. after the last byte of the command sequence has been clocked in, then three address bytes specifying any address within the sec- tor to be locked down must be clocked into the device. after the last address bit has been clocked in, the cs pin must then be deasserted to initiate the internally self-timed lockdown sequence. the lockdown sequence should take place in a maximum time of t p , during which time the status register will indicate that the device is busy. if the device is powered-down before the comple- tion of the lockdown sequence, then the lockdown status of the sector cannot be guaranteed. in this case, it is recommended that the user read the sector lockdown register to determine the status of the appropriate sector lockdown bits or bytes and reissue the sector lockdown com- mand if necessary. figure 10-1. sector lockdown command byte 1 byte 2 byte 3 byte 4 sector lockdown 3dh 2ah 7fh 30h opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs address bytes address bytes address bytes each transition represents 8 bits si
19 3597o?dflash?10/09 at45db321d 10.1.1 sector lockdown register sector lockdown register is a nonvolatile regist er that contains 64 bytes of data, as shown below: 10.1.2 reading the sector lockdown register the sector lockdown register can be read to determine which sectors in the memory array are permanently locked down. to read the sector lockdown register, the cs pin must first be asserted. once the cs pin has been asserted, an opcode of 35h and 3 dummy bytes must be clocked into the device via the si pin. after the last bit of the opcode and dummy bytes have been clocked in, the data for the contents of the sector lockdown register will be clocked out on the so pin. the first byte corresponds to sector 0 (0a, 0b) the second byte corresponds to sector 1 and the last byte (byte 16) corresponds to sector 15. after the last byte of the sector lockdown register has been read, additional pulses on the sck pin will simply result in unde- fined data being output on the so pin. deasserting the cs pin will terminate the read sector lockdown regist er operation and put the so pin into a high-impedance state. table 10-2 details the values read from the sector lockdown register. figure 10-2. read sector lockdown register sector number 0 (0a, 0b) 1 to 63 locked see below ffh unlocked 00h table 10-1. sector 0 (0a, 0b) 0a 0b bit 3, 2 data value (pages 0-7) (pages 8-127) bit 7, 6 bit 5, 4 bit 1, 0 sectors 0a, 0b unlocked 00 00 00 00 00h sector 0a locked (pages 0-7) 11 00 00 00 c0h sector 0b locked (pages 8-127) 00 11 00 00 30h sectors 0a, 0b locked (pages 0-127) 11 11 00 00 f0h table 10-2. sector lockdown register command byte 1 byte 2 byte 3 byte 4 read sector lockdown register 35h xxh xxh xxh note: xx = dummy byte opcode x x x d a t a byte n d a t a byte n + 1 c s d a t a byte n + 6 3 s i s o e a ch tr a n s ition repre s ent s 8 b it s
20 3597o?dflash?10/09 at45db321d 10.2 security register the device contains a specialized security register that can be used for purposes such as unique device serialization or locked key storage. the register is comprised of a total of 128 bytes that is divided into two portions. the first 64 bytes (byte locations 0 through 63) of the security register are allocated as a one-time user programmable space. once these 64 bytes have been programmed, they cannot be reprogrammed. the remaining 64 bytes of the register (byte locations 64 through 127) are factory programmed by atmel and will contain a unique value for each device. the factory programmed data is fixed and cannot be changed. 10.2.1 programming the security register the user programmable portion of the security register does not need to be erased before it is programmed. to program the security register, the cs pin must first be asserted and the appropriate 4-byte opcode sequence must be clocked into the devic e in the correct order. the 4-byte opcode sequence must start with 9bh and be followed by 00h, 00h, and 00h. after the last bit of the opcode sequence has been clocked into the device, the data for the contents of the 64-byte user programmable portion of the security register must be clocked in. after the last data byte has been clocked in, the cs pin must be deasserted to initiate the inter- nally self-timed program cycle. the programming of the security register should take place in a time of t p , during which time the status register will indi cate that the device is busy. if the device is powered-down during the program cycle, then the contents of the 64-byte user programmable portion of the security register cannot be guaranteed. if the full 64 bytes of data is not clocked in before the cs pin is deasserted, then the values of the byte locations not clocked in cannot be guaranteed. for example, if only the first two bytes are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the user pro- grammable portion of the security register cannot be guaranteed. furthermore, if more than 64 bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. for instance, if 65 bytes of data are clocked in, t hen the 65th byte will be stored at byte location 0 of the security register. the user programmable portion of the security register can only be programmed one time. therefore, it is not possible to only program the first two bytes of the register and then pro- gram the remaining 62 bytes at a later time. the program security register command utilizes the internal sram buffer 1 for processing. therefore, the contents of the buffer 1 will be alte red from its previous state when this command is issued. figure 10-3. program security register table 10-3. security register security register byte number 01 ? ? ? 62 63 64 65 ? ? ? 126 127 data type one-time user programmable factory programmed by atmel data byte n opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 data byte n + 1 data byte n + x cs each transition represents 8 bits si
21 3597o?dflash?10/09 at45db321d 10.2.2 reading the security register the security register can be read by first asserting the cs pin and then clocking in an opcode of 77h followed by three dummy bytes. after the last don't care bit has been clocked in, the con- tent of the security register can be clocked out on the so pins. after the last byte of the security register has been read , additional pulses on the sck pi n will simply result in undefined data being output on the so pins. deasserting the cs pin will terminate the read security register operation and put the so pins into a high-impedance state. figure 10-4. read security register 11. additional commands 11.1 main memory page to buffer transfer a page of data can be transferred from the main memory to either buffer 1 or buffer 2. to start the operation for the dataflash standard page size (528 bytes), a 1-byte opcode, 53h for buffer 1 and 55h for buffer 2, must be clocked into the device, followed by three address bytes com- prised of 1 don?t care bit, 13-page address bit (pa12 - pa0), which specify the page in main memory that is to be transferred, and 10 don?t care bits. to perform a main memory page to buf- fer transfer for the binary page size (512 bytes), the opcode 53h for buffer 1 or 55h for buffer 2, must be clocked into the device followed by thre e address bytes consisting of 2 don?t care bits, 13-page address bits (a21 - a9) which specify the page in the main memory that is to be trans- ferred, and 9 don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode and the address bytes from the input pin (si). the transfer of the page of data from the main memory to the buffer will begin when the cs pin transitions from a low to a high state. dur- ing the transfer of a page of data (t xfr ), the status register can be read or the rdy/busy can be monitored to determine whether the transfer has been completed. opcode x x x data byte n data byte n + 1 cs data byte n + x each transition represents 8 bits si so
22 3597o?dflash?10/09 at45db321d 11.2 main memory page to buffer compare a page of data in the main memory can be compared to the data in buffer 1 or buffer 2. to initi- ate the operation for dataflash standard page size, a 1-byte opcode, 60h for buffer 1 and 61h for buffer 2, must be clocked into the device, followed by three address bytes consisting of 1 don?t care bit, 13-page address bits (pa12 - pa0) that specify the page in the main memory that is to be compared to the buffer, and 10 don?t care bits. to start a main memory page to buf- fer compare for a binary page size, the opcode 60h for buffer 1 or 61h for buffer 2, must be clocked into the device followed by three address bytes consisting of 2 don?t care bits, 13 page address bits (a21 - a9) that specify the page in the main memory that is to be compared to the buffer, and 9 don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode and the address bytes from the input pin (si). on the low-to-high transition of the cs pin, the data bytes in the selected main memory page will be compared with the data bytes in buffer 1 or buffer 2. during this time (t comp ), the status register and the rdy/busy pin will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register is updated with the result of the compare. 11.3 auto page rewrite this mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion within a sector. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. to start the rewrite operation for the dataflash standard page size (528 bytes), a 1-byte opcode, 58h for buffer 1 or 59h for buffer 2, must be clocked into the device, followed by three address bytes comprised of 1 don?t care bit, 13-page address bits (pa12-pa0) that specify the page in main memory to be rewritten and 10 don?t care bits. to initiate an auto page rewrite for a binary page size (512 bytes), the opcode 58h for buffer 1 or 59h for buffer 2, must be clocked into the device followed by three address bytes consisting of 2 don?t care bits, 13 page address bits (a21 - a9) that specify the page in the main memory that is to be written and 9 don?t care bits. when a low- to-high transition occurs on the cs pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the status register and the rdy/busy pin will indicate that the part is busy. if a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in figure 25-1 ( page 46 ) is recommended. otherwise , if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in figure 25-2 ( page 47 ) is recommended. each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector.
23 3597o?dflash?10/09 at45db321d 11.4 status register read the status register can be used to determine the device?s ready/busy status, page size, a main memory page to buffer compare operation result, the sector protection status or the device density. the status register can be read at any time, including during an internally self-timed program or erase operation. to read the status register, the cs pin must be asserted and the opcode of d7h must be loaded into the device. after the opcode is clocked in, the 1-byte status register will be clocked out on the output pin (so) , starting with the next clock cycle. the data in the status register, starting wi th the msb (bit 7), will be clock ed out on the so pi n during the next eight clock cycles. after the one byte of the st atus register has been clocked out, the sequence will repeat itself (as long as cs remains low and sck is being toggled). the data in the status register is constantly updated, so each repeating sequence will output new data. ready/busy status is indicated using bit 7 of the st atus register. if bit 7 is a 1, then the device is not busy and is ready to accept the next command. if bit 7 is a 0, then the device is in a busy state. since the data in the status register is constantly updated, the user must toggle sck pin to check the ready/busy status. there are several operations that can cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer compare, buf- fer to main memory page program, main memory page program through buffer, page erase, block erase, sector erase, chip erase and auto page rewrite. the result of the most recent main memory page to buffer compare operation is indicated using bit 6 of the status register. if bit 6 is a 0, then the data in the main memory page matches the data in the buffer. if bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. bit 1 in the status register is used to provide information to the user whether or not the sector protection has been enabled or disabled, either by software-controlled method or hardware-con- trolled method. a logic 1 indicates that sector protection has been enabled and logic 0 indicates that sector protection has been disabled. bit 0 in the status register indicates whether the page size of the main memory array is config- ured for ?power of 2? binary page size (512 by tes) or dataflash standard page size (528 bytes). if bit 0 is a 1, then the page size is set to 512 bytes. if bit 0 is a 0, then the page size is set to 528 bytes. the device density is indicated using bits 5, 4, 3, and 2 of the status register. for the at45db321d, the four bits are 1101 the decimal va lue of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of dataflash devices. the device density is not the same as the density code indicated in the jedec device id information. the device densit y is provided only for backward compatibility. table 11-1. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp 1 1 0 1 protect page size
24 3597o?dflash?10/09 at45db321d 12. deep power-down after initial power-up, the device will default in standby mode. the deep po wer-down command allows the device to enter into the lowest power consumption mode. to enter the deep power- down mode, the cs pin must first be asserted. once the cs pin has been asserted, an opcode of b9h command must be clocked in via input pin (si). after the last bit of the command has been clocked in, the cs pin must be de-asserted to initiate the deep power-down operation. after the cs pin is de-asserted, the device will ente r the deep power-down mode within the maximum t edpd time. once the device has entered the deep power-down mode, all instructions are ignored except for the resume from deep power-down command. figure 12-1. deep power-down 12.1 resume from deep power-down the resume from deep power-down command takes the device out of the deep power-down mode and returns it to the normal standby mode. to resume from deep power-down mode, the cs pin must first be asserted and an opcode of abh command must be clocked in via input pin (si). after the last bit of the command has been clocked in, the cs pin must be de-asserted to terminate the deep power-down mode. after the cs pin is de-asserted, the device will return to the normal standby mode within the maximum t rdpd time. the cs pin must remain high during the t rdpd time before the device can receive any commands. after resuming form deep power- down, the device w ill return to the nor mal standby mode. figure 12-2. resume from deep power-down command opcode deep power-down b9h opcode cs each transition represents 8 bits si command opcode resume from deep power-down abh opcode cs each transition represents 8 bits si
25 3597o?dflash?10/09 at45db321d 13. ?power of 2? binary page size option ?power of 2? binary page size configuration regi ster is a user-programmable nonvolatile regis- ter that allows the page size of the main memory to be configured for binary page size (512 bytes) or dataflash standard page size (528 bytes). the ?power of 2? page size is a one- time programmable configuration register and once the device is configured for ?power of 2? page size, it cannot be reconfigured again. the devices are initially shipped with the page size set to 528 bytes. the user has the option of ordering binary page size (512 bytes) devices from the factory. for details, please refer to section 26. ?ordering information? on page 48 . for the binary ?power of 2? page size to become effective, the following steps must be followed: 1. program the one-time programmable configuration resister using opcode sequence 3dh, 2ah, 80h and a6h (please see section 13.1 ). 2. power cycle the device (i.e. power down and power up again). 3. the page for the binary page size can now be programmed. if the above steps are not followed to set the page size prior to page programming, incorrect data during a read operation may be encountered. 13.1 programming the c onfiguration register to program the configuration register for ?power of 2? binary page size, the cs pin must first be asserted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. the 4-byte opcode sequence must start with 3dh and be followed by 2ah, 80h, and a6h. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initiate the internally self-timed prog ram cycle. the programming of th e configuration register should take place in a time of t p , during which time the status regist er will indicate that the device is busy. the device must be power cycled after the completion of the program cycle to set the ?power of 2? page size. if the device is powered-down before the completion of the program cycle, then setting the configuration register cannot be guaranteed. however, the user should check bit 0 of the status register to see w hether the page size was configured for binary page size. if not, the command can be re-issued again. figure 13-1. erase sector protection register command byte 1 byte 2 byte 3 byte 4 power of two page size 3dh 2ah 80h a6h opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si
26 3597o?dflash?10/09 at45db321d 14. manufacturer an d device id read identification information can be read from the dev ice to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jedec defined manufacturer id, the vendor specific device id, and the ven- dor specific extended device information. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opc ode has been clocked in, the device will begin out- putting the identification data on the so pin during the subsequent cloc k cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fourth byte ou tput will be the extended device informat ion string length, which will be 00h indicating that no extended device information follows. as indi cated in the jedec standard, reading the extended device information string length and any subsequent data is optional. deasserting the cs pin will terminate the manufacturer a nd device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. 14.1 manufacturer and device id information 14.1.1 byte 1 ? manufacturer id hex value jedec assigned code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1fh 0 0 0 1 1 1 1 1 manufacturer id 1fh = atmel 14.1.2 byte 2 ? device id (part 1) hex value family code density code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 family code 001 = dataflash 27h 0 0 1 0 0 1 1 1 density code 00111 = 32-mbit 14.1.3 byte 3 ? device id (part 2) hex value mlc code product version code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mlc code 000 = 1-bit/cell technology 00h 0 0 0 0 0 0 0 1 product version 00001 = second version 14.1.4 byte 4 ? extended device information string length hex value byte count bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h 0 0 0 0 0 0 0 0 byte count 00h = 0 bytes of information
27 3597o?dflash?10/09 at45db321d note: based on jedec publication 106 (jep106), ma nufacturer id data can be comprised of any number of bytes. some manufacturers may have manufacturer id codes that are two, three or even four byte s long with the first byte(s) in the sequence being 7fh. a system sh ould detect code 7fh as a ?continuation code? and continue to read manufacturer id bytes. the first non-7fh byte w ould signify the last byte of manufacturer id data. for atmel (and some other manufacturers), the manufacturer id data is comprised of only one byte. 14.2 operation m ode summary the commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. group a commands consist of: 1. main memory page read 2. continuous array read 3. read sector protection register 4. read sector lockdown register 5. read security register group b commands consist of: 1. page erase 2. block erase 3. sector erase 4. chip erase 5. main memory page to buffer 1 (or 2) transfer 6. main memory page to buffer 1 (or 2) compare 7. buffer 1 (or 2) to main memory page program with built-in erase 8. buffer 1 (or 2) to main memory page program without built-in erase 9. main memory page program through buffer 1 (or 2) 10. auto page rewrite group c commands consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status register read 4. manufacturer and device id read 9fh manufacturer id byte 1 device id byte 2 device id byte 3 this information would only be output if the extended device information string length value was something other than 00h. extended device information string length extended device information byte x extended device information byte x + 1 cs 1fh 27h 00h 01h data data si so opcode each transition represents 8 bits
28 3597o?dflash?10/09 at45db321d group d commands consist of: 1. erase sector protection register 2. program sector protection register 3. sector lockdown 4. program security register if a group a command is in progress (not fully completed), then another command in group a, b, c, or d should not be started. however, during the internally self-timed portion of group b commands, any command in group c can be executed. the group b commands using buffer 1 should use group c commands using buffer 2 and vi ce versa. finally, during the internally self- timed portion of a group d command, only the status register read command should be executed. 15. command tables table 15-1. read commands command opcode main memory page read d2h continuous array read (legacy command) e8h continuous array read (low frequency) 03h continuous array read (high frequency) 0bh buffer 1 read (low frequency) d1h buffer 2 read (low frequency) d3h buffer 1 read d4h buffer 2 read d6h table 15-2. program and erase commands command opcode buffer 1 write 84h buffer 2 write 87h buffer 1 to main memory page program with built-in erase 83h buffer 2 to main memory page program with built-in erase 86h buffer 1 to main memory page program without built-in erase 88h buffer 2 to main memory page program without built-in erase 89h page erase 81h block erase 50h sector erase 7ch chip erase c7h, 94h, 80h, 9ah main memory page program through buffer 1 82h main memory page program through buffer 2 85h
29 3597o?dflash?10/09 at45db321d note: 1. these legacy commands are not recommended for new designs. table 15-3. protection and security commands command opcode enable sector protection 3dh + 2ah + 7fh + a9h disable sector protection 3dh + 2ah + 7fh + 9ah erase sector protection register 3dh + 2ah + 7fh + cfh program sector protection register 3dh + 2ah + 7fh + fch read sector protection register 32h sector lockdown 3dh + 2ah + 7fh + 30h read sector lockdown register 35h program security register 9bh + 00h + 00h + 00h read security register 77h table 15-4. additional commands command opcode main memory page to buffer 1 transfer 53h main memory page to buffer 2 transfer 55h main memory page to buffer 1 compare 60h main memory page to buffer 2 compare 61h auto page rewrite through buffer 1 58h auto page rewrite through buffer 2 59h deep power-down b9h resume from deep power-down abh status register read d7h manufacturer and device id read 9fh table 15-5. legacy commands (1) command opcode buffer 1 read 54h buffer 2 read 56h main memory page read 52h continuous array read 68h status register read 57h
30 3597o?dflash?10/09 at45db321d notes: x = don?t care table 15-6. detailed bit-level addressing sequence for binary page size (512 bytes) page size = 512 bytes address byte address byte address byte additional don?t care bytes opcode opcode reserved reserved a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 03h 0000001 1 xx aaaaa a aaaaaaa a aaaaaaa a n/a 0bh 0000101 1 xx aaaaa a aaaaaaa a aaaaaaa a 1 50h 0101000 0 xx aaaaa a aaaax x x x x x xxxxx x n/a 53h 0101001 1 xx aaaaa a aaaaaaa x x x xxxxx x n/a 55h 0101010 1 xx aaaaa a aaaaaaa x x x xxxxx x n/a 58h 0101100 0 xx aaaaa a aaaaaaa x x x xxxxx x n/a 59h 0101100 1 xx aaaaa a aaaaaaa x x x xxxxx x n/a 60h 0110000 0 xx aaaaa a aaaaaaa x x x xxxxx x n/a 61h 0110000 1 xx aaaaa a aaaaaaa x x x xxxxx x n/a 77h 0111011 1 xxx xxxx x xxxxxxx x xxxxxxx x n/a 7ch 0111110 0 xx aaaaa a x x xxxxx x xxxxxxx x n/a 81h 1000000 1 xx aaaaa a aaaaaaa x x x xxxxx x n/a 82h 1000001 0 xx aaaaa a aaaaaaa a aaaaaaa a n/a 83h 1000001 1 xx aaaaa a aaaaaaa x x x xxxxx x n/a 84h 1000010 0 xxx xxxx x xxxxxxxaa aaaaaa a n/a 85h 1000010 1 xx aaaaa a aaaaaaa a aaaaaaa a n/a 86h 1000011 0 xx aaaaa a aaaaaaa x x x xxxxx x n/a 87h 1000011 1 xxx xxxx x xxxxxxxaa aaaaaa a n/a 88h 1000100 0 xx aaaaa a aaaaaaa x x x xxxxx x n/a 89h 1000100 1 xx aaaaa a aaaaaaa x x x xxxxx x n/a 9fh 1001111 1 n/a n/a n/a n/a b9h 1011100 1 n/a n/a n/a n/a abh 1010101 1 n/a n/a n/a n/a d1h 1101000 1 xxx xxxx x xxxxxxxaa aaaaaa a n/a d2h 1101001 0 xx aaaaa a aaaaaaa a aaaaaaa a 4 d3h 1101001 1 xxx xxxx x xxxxxxxaa aaaaaa a n/a d4h 1101010 0 xxx xxxx x xxxxxxxaa aaaaaa a 1 d6h 1101011 0 xxx xxxx x xxxxxxxaa aaaaaa a 1 d7h 1101011 1 n/a n/a n/a n/a e8h 1110100 0 xx aaaaa a aaaaaaa a aaaaaaa a 4
31 3597o?dflash?10/09 at45db321d notes: p = page address bit b = byte/buffer address bit x = don?t care table 15-7. detailed bit-level addressing sequence for dataflash standard page size (528 bytes) page size = 528 bytes address byte address byte address byte additional don?t care bytes opcode opcode reserved pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ba9 ba8 ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0 03h 0 0 0 0 0 0 1 1 xpppppp p ppppppb b bbbbbbb b n/a 0bh 0 0 0 0 1 0 1 1 xpppppp p ppppppb b bbbbbbb b 1 50h 0101000 0 xppppppppppxxxx x xxxxxxx x n/a 53h 0 1 0 1 0 0 1 1 xpppppp p ppppppx x x x x x x x x x n/a 55h 0 1 0 1 0 1 0 1 xpppppp p ppppppx x x x x x x x x x n/a 58h 0 1 0 1 1 0 0 0 xpppppp p ppppppx x x x x x x x x x n/a 59h 0 1 0 1 1 0 0 1 xpppppp p ppppppx x x x x x x x x x n/a 60h 0 1 1 0 0 0 0 0 xpppppp p ppppppx x x x x x x x x x n/a 61h 0 1 1 0 0 0 0 1 xpppppp p ppppppx x x x x x x x x x n/a 77h 0111011 1 xxxxxxx x xxxxxxx x xxxxxxx x n/a 7ch 0111110 0 xppppppx xxxxxxx x xxxxxxx x n/a 81h 1 0 0 0 0 0 0 1 xpppppp p ppppppx x x x x x x x x x n/a 82h 1 0 0 0 0 0 1 0 xpppppp p ppppppb b bbbbbbb b n/a 83h 1 0 0 0 0 0 1 1 xpppppp p ppppppx x x x x x x x x x n/a 84h 1000010 0 xxxxxxx x xxxxxxbbbbbbbbb b n/a 85h 1 0 0 0 0 1 0 1 xpppppp p ppppppb b bbbbbbb b n/a 86h 1 0 0 0 0 1 1 0 xpppppp p ppppppx x x x x x x x x x n/a 87h 1000011 1 xxxxxxx x xxxxxxbbbbbbbbb b n/a 88h 1 0 0 0 1 0 0 0 xpppppp p ppppppx x x x x x x x x x n/a 89h 1 0 0 0 1 0 0 1 xpppppp p ppppppx x x x x x x x x x n/a 9fh 1001111 1 n/a n/a n/a n/a b9h 1011100 1 n/a n/a n/a n/a abh 1010101 1 n/a n/a n/a n/a d1h 1101000 1 xxxxxxx x xxxxxxbbbbbbbbb b n/a d2h 1 1 0 1 0 0 1 0 xpppppp p ppppppb b bbbbbbb b 4 d3h 1101000 1 xxxxxxx x xxxxxxbbbbbbbbb b n/a d4h 1101010 0 xxxxxxx x xxxxxxbbbbbbbbb b 1 d6h 1101011 0 xxxxxxx x xxxxxxbbbbbbbbb b 1 d7h 1101011 1 n/a n/a n/a n/a e8h 1 1 1 0 1 0 0 0 xpppppp p ppppppb b bbbbbbb b 4
32 3597o?dflash?10/09 at45db321d 16. power-on/reset state when power is first applied to the device, or when recovering from a reset condition, the device will default to mode 3. in additi on, the output pin (so) will be in a high impedance state, and a high-to-low transition on the cs pin will be required to start a va lid instruction. the mode (mode 3 or mode 0) will be automatically selected on every falling edge of cs by sampling the inactive clock state. 16.1 initial power-up/re set timing restrictions at power up, the device must not be selected until the supply voltage reaches the v cc (min.) and further delay of t vcsl . during power-up, the internal power-on reset circuitry keeps the device in reset mode until the v cc rises above the power-on reset threshold value (v por ). at this time, all operations are disabled and the device does not respond to any commands. after power up is applied and the v cc is at the minimum operating voltage v cc (min.), the t vcsl delay is required before the device can be selected in order to perform a read operation. similarly, the t puw delay is required after the v cc rises above the power-on reset threshold value (v por ) before the device can perform a write (program or erase) operation. after initial power-up, the device will de fault in standby mode. 17. system considerations the rapids serial interface is controlled by the clock sck, serial input si and chip select cs pins. these signals must rise and fall monotonica lly and be free from noise. excessive noise or ringing on these pins can be mi sinterpreted as multiple edges and cause improper operation of the device. the pc board traces must be kept to a minimum distance or appropriately termi- nated to ensure proper operation. if necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. as system complexity continues to increase, voltage regulation is becoming more important. a key element of any voltage regulation scheme is its current sourcing capability. like all flash memories, the peak current for dataflash occur during the programming and erase operation. the regulator needs to supply this peak current requirement. an under specified regulator can cause current starvation. besides increasing sy stem noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. symbol parameter min typ max units t vcsl v cc (min.) to chip select low 70 s t puw power-up device delay before write allowed 20 ms v por power-on reset voltage 1.5 2.5 v
33 3597o?dflash?10/09 at45db321d 18. electrical specifications table 18-1. absolute maximum ratings* temperature under bias .... ........... ............ .... -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. the "absolute maximum rat- ings" are stress ratings only and functional operation of the device at these or any other con- ditions beyond those indicated in the operational sections of this specificat ion is not implied. expo- sure to absolute maximum rating conditions for extended periods may affect device reliability. voltage extremes referenced in the "absolute maximum ratings" are intended to accommo- date short duration undershoot/overshoot condi- tions and does not imply or guarantee functional device operation at these levels for any extended period of time storage temperature .................................... -65 c to +150 c all input voltages (except v cc but including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v table 18-2. dc and ac operating range at45db321d (2.5v version) at45db321d operating temperature (case) -40c to 85c -40 c to 85 c v cc power supply 2.5v to 3.6v 2.7v to 3.6v
34 3597o?dflash?10/09 at45db321d notes: 1. i cc1 during a buffer read is 20 ma maximum @ 20 mhz. 2. all inputs (si, sck, cs#, wp#, and reset#) ar e guaranteed by design to be 5-volt tolerant. table 18-3. dc characteristics symbol parameter condition min typ max units i dp deep power-down current cs , reset , wp = v ih , all inputs at cmos levels 15 25 a i sb standby current cs , reset , wp = v ih , all inputs at cmos levels 25 50 a i cc1 (1) active current, read operation f = 20 mhz; i out = 0 ma; v cc = 3.6v 710ma f = 33 mhz; i out = 0 ma; v cc = 3.6v 812ma f = 50 mhz; i out = 0 ma; v cc = 3.6v 10 14 ma f = 66 mhz; i out = 0 ma; v cc = 3.6v 11 15 ma i cc2 active current, program/erase operation v cc = 3.6v 12 17 ma i li input load current v in = cmos levels 1 a i lo output leakage current v i/o = cmos levels 1 a v il input low voltage v cc x 0.3 v v ih input high voltage v cc x 0.7 v v ol output low voltage i ol = 1.6 ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v
35 3597o?dflash?10/09 at45db321d table 18-4. ac characteristics ? rapids/serial interface symbol parameter at45db321d (2.5v version) at45db321d min typ max min typ max units f sck sck frequency 50 66 mhz f car1 sck frequency for continuous array read 50 66 mhz f car2 sck frequency for continuous array read (low frequency) 33 33 mhz t wh sck high time 6.8 6.8 ns t wl sck low time 6.8 6.8 ns t sckr (1) sck rise time, peak-to-peak (slew rate) 0.1 0.1 v/ns t sckf (1) sck fall time, peak-to-peak (slew rate) 0.1 0.1 v/ns t cs minimum cs high time 50 50 ns t css cs setup time 5 5 ns t csh cs hold time 5 5 ns t csb cs high to rdy/busy low 100 100 ns t su data in setup time 2 2 ns t h data in hold time 3 3 ns t ho output hold time 0 0 ns t dis output disable time 27 35 27 35 ns t v output valid 8 6 ns t wpe wp low to protection enabled 1 1 s t wpd wp high to protection disabled 1 1 s t edpd cs high to deep power-down mode 3 3 s t rdpd cs high to standby mode 35 35 s t xfr page to buffer transfer time 200 200 s t comp page to buffer compare time 200 200 s t ep page erase and programming time (512/528 bytes) 17 40 17 40 ms t p page programming time (512/528 bytes) 3 6 3 6 ms t pe page erase time (512/528 bytes) 15 35 15 35 ms t be block erase time (4,096/4,224 bytes) 45 100 45 100 ms t ce chip erase time 1.6 5 1.6 5 s t se sector erase time (131,072/135,168 bytes) tbd tbd tbd tbd s t rst reset pulse width 10 10 s t rec reset recovery time 1 1 s
36 3597o?dflash?10/09 at45db321d 19. input test waveform s and measurement levels t r , t f < 2 ns (10% to 90%) 20. output test load 21. ac waveforms six different timing waveforms are shown on page 37 . waveform 1 shows the sck signal being low when cs makes a high-to-low transition, and waveform 2 shows the sck signal being high when cs makes a high-to-low transition. in both cases, output so becomes valid while the sck signal is still low (sck lo w time is specified as t wl ). timing waveforms 1 and 2 conform to rapids serial interface but for frequencies up to 66 mhz. waveforms 1 and 2 are compatible with spi mode 0 and spi mode 3, respectively. waveform 3 and waveform 4 illustra te general timing diagram for r apids serial interface. these are similar to waveform 1 and waveform 2, except that output so is not restricted to become valid during the t wl period. these timing waveforms are valid over the full frequency range (max- imum frequency = 66 mhz) of the rapids serial case. ac dri v i n g le v els ac measureme n t le v el 0.45 v 1.5 v 2.4 v device under test 30 pf
37 3597o?dflash?10/09 at45db321d 21.1 waveform 1 ? spi mode 0 compat ible (for frequencies up to 66 mhz) 21.2 waveform 2 ? spi mode 3 compat ible (for frequencies up to 66 mhz) 21.3 waveform 3 ? rapids mode 0 (f max = 66 mhz) 21.4 waveform 4 ? rapids mode 3 (f max = 66 mhz) cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance si cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance si
38 3597o?dflash?10/09 at45db321d 21.5 utilizing the rapids ? function to take advantage of the rapids function's abili ty to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. the dataflash is designed to always clock its data out on the falling edge of the sck signal and clock data in on the rising edge of sck. for full clock cycle operation to be achieved, when the dataflash is clocking data out on the fall- ing edge of sck, the host controller should wait until the next falling edge of sck to latch the data in. similarly, the host controller should clock its data out on the rising edge of sck in order to give the dataflash a full clock cycle to latc h the incoming data in on the next rising edge of sck. figure 21-1. rapids mode sck mosi miso 1 234567 81 234567 8 mosi = master out, slave in miso = master in, slave out the master is the host controller and the slave is the dataflash the master always clocks data out on the rising edge of sck and always clocks data in on the falling edge of sck. the slave always clocks data out on the falling edge of sck and always clocks data in on the rising edge of sck. a. master clocks out first bit of byte-mosi on the rising edge of sck. b. slave clocks in first bit of byte-mosi on the next rising edge of sck. c. master clocks out second bit of byte-mosi on the same rising edge of sck. d. last bit of byte-mosi is clocked out from the master. e. last bit of byte-mosi is clocked into the slave. f. slave clocks out first bit of byte-so. g. master clocks in first bit of byte-so. h. slave clocks out second bit of byte-so. i. master clocks in last bit of byte-so. a b cd e f g 1 h byte-mosi msb lsb byte-so msb lsb slave cs i
39 3597o?dflash?10/09 at45db321d 21.6 reset timing note: the cs signal should be in th e high state before the reset signal is deasserted. 21.7 command sequence for read/write operations for page size 512 bytes (e xcept status register read, manufact urer and device id read) 21.8 command sequence for read/write operations for page size 528 bytes (e xcept status register read, manufact urer and device id read) cs sck reset so (output) high impedance high impedance si (input) t rst t rec t css s i (input) cmd 8 b it s 8 b it s 8 b it s p a ge addre ss (a21 - a9) x x x x x x x x x x x x x x x x l s b x x x x x x x x byte/b u ffer addre ss (a 8 - a0/bfa 8 - bfa0) m s b don ? t c a re bit s p a ge addre ss (pa12 - pa0) byte/b u ffer addre ss (ba9 - ba0/bfa9 - bfa0) s i (input) cmd 8 b it s 8 b it s 8 b it s x x x xx x x x x x x x l s b x x x x x x x x m s b 1 don ? t c a re bit x x x x
40 3597o?dflash?10/09 at45db321d 22. write operations the following block diagram and waveforms illustra te the various write sequences available. 22.1 buffer write 22.2 buffer to main memory page program (dat a from buffer progra mmed into flash page) flash memory array page (512/528 bytes) buffer 2 (512/528 bytes) buffer 1 (512/528 bytes) i/o interface si buffer 1 to main memory page program buffer 2 to main memory page program buffer 1 write buffer 2 write si (input) cmd completes writing into selected buffer cs x xx, bfa9-8 bfa7-0 n n+1 last byte binary page size 15 don't care + bfa8-bfa0 s i (input) cmd pa12-6 pa5-0, xx c s s t a rt s s elf-timed er as e/progr a m oper a tion xxxx xx e a ch tr a n s ition repre s ent s 8 b it s n = 1 s t b yte re a d n+1 = 2nd b yte re a d binary page s ize a21-a9 + 9 don't care bit s
41 3597o?dflash?10/09 at45db321d 23. read operations the following block diagram and waveforms illustra te the various read sequences available. 23.1 main memory page read 23.2 main memory page to buffer transfer (data from flash page read into buffer) flash memory array page (512/528 bytes) buffer 2 (512/528 bytes) buffer 1 (512/528 bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read so s i (input) cmd pa12-6 pa5-0, ba9- 8 x c s n n+1 s o (output) ba7-0 4 d u mmy byte s x addre ss for binary page s ize a21-a16 a15-a 8 a7-a0 s t a rt s re a ding p a ge d a t a into bu ffer s i (input) cmd pa12-6 pa5-0, xx c s s o (output) xxxx xxxx binary page s ize a21-a9 + 9 don't care bit s
42 3597o?dflash?10/09 at45db321d 23.3 buffer read 24. detailed bit-level read waveform ? ra pids serial interface mode 0/mode 3 24.1 continuous array read (legacy opcode e8h) 24.2 continuous arra y read (opcode 0bh) cmd cs n n+1 x x x..x, bfa9-8 bfa7- 0 binary page size 15 don't care + bfa8-bfa0 each transition represents 8 bits si (input) so (output) no dummy byte (opcodes d1h and d3h) 1 dummy byte (opcodes d4h and d6h) sck cs si so msb msb 23 1 0 11101000 67 5 41011 9 812 636667 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode aaaa aaa aa msb xxxx xx msb msb dddddddd d d address bits 32 don't care bits data byte 1 high-impedance bit 4095/4223 of page n bit 0 of page n+1 s ck c s s i s o m s bm s b 2 3 1 0 00001011 67 5 41011 9 8 12 3 9424 3 41 40 38 33 3 4 3 1 3 2 29 3 044474 8 46 45 opcode aaaa aaa aa m s b xxxx xx m s bm s b dddddddd d d addre ss bit s a21 - a0 don't care data byte 1 high-impedance 3 6 3 7 3 5 x x
43 3597o?dflash?10/09 at45db321d 24.3 continuous array read (low frequency: opcode 03h) 24.4 main memory pa ge read (opcode: d2h) 24.5 buffer read (opcode d4h or d6h) s ck c s s i s o m s bm s b 2 3 1 0 00000011 67 5 41011 9 8 12 3 7 38 33 3 6 3 5 3 4 3 1 3 2 29 3 0 3 940 opcode aaaa aaa aa m s bm s b dddddddd d d addre ss bit s a21-a0 data byte 1 high-impedance sck cs si so msb msb 23 1 0 11010010 67 5 41011 9 812 636667 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode aaaa aaa aa msb xxxx xx msb msb dddddddd d d address bits 32 don't care bits data byte 1 high-impedance sck cs si so msb msb 23 1 0 11010100 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode xxxx aaa xx msb xxxxxxxx msb msb dddddddd d d address bits binary page size = 15 don't care + bfa8-bfa0 standard dataflash page size = 14 don't care + bfa9-bfa0 don't care data byte 1 high-impedance
44 3597o?dflash?10/09 at45db321d 24.6 buffer read (low frequ ency: opcode d1h or d3h) 24.7 read sector protecti on register (opcode 32h) 24.8 read sector lockdow n register (opcode 35h) sck cs si so msb msb 23 1 0 11010001 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx aaa xx msb msb dddddddd d d data byte 1 high-impedance address bits binary page size = 15 don't care + bfa8-bfa0 standard dataflash page size = 14 don't care + bfa9-bfa0 sck cs si so msb msb 23 1 0 00110010 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx xxx xx msb msb ddddddd d d don't care data byte 1 high-impedance sck cs si so msb msb 23 1 0 00110101 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx xxx xx msb msb ddddddd d d don't care data byte 1 high-impedance
45 3597o?dflash?10/09 at45db321d 24.9 read security r egister (opcode 77h) 24.10 status register read (opcode d7h) 24.11 manufacturer and device read (opcode 9fh) sck cs si so msb msb 23 1 0 01110111 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx xxx xx msb msb ddddddd d d don't care data byte 1 high-impedance s ck c s s i s o m s b 2 3 1 0 11010111 67 5 41011 9 8 12 21 22 17 20 19 1 8 15 16 1 3 14 2 3 24 opcode m s b m s b dddddd dd d d m s b dddddd d d s tat u s regi s ter data s tat u s regi s ter data high-impedance sck cs si so 6 0 9fh 8 7 38 opcode 1fh device id byte 1 device id byte 2 00h high-impedance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits)
46 3597o?dflash?10/09 at45db321d 25. auto page rewrite flowchart figure 25-1. algorithm for programming or reprogramming of the entire array sequentially notes: 1. this type of algorithm is used for applications in wh ich the entire array is programmed sequentially, filling the array page-by- page. 2. a page can be written using either a main memory page prog ram operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. start mai n memory page program through buffer ( 8 2h, 8 5h) e n d pro v ide address and data buffer w rite ( 8 4h, 8 7h) buffer to mai n memory page program ( 8 3h, 8 6h)
47 3597o?dflash?10/09 at45db321d figure 25-2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of a dataflash se ctor must be updated/rewritten at least once within every 10,000 cumulative page erase and program operations. 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite portions of the flash array. low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. see application note an-4 (?using atmel?s serial dataflash?) for more details. start mai n memory page to buffer tra n sfer (53h, 55h) i n creme n t page address poi n ter (2) auto page re w rite (2) (5 8 h, 59h) e n d pro v ide address of page to modify if planning to modify m u ltiple b ytes c u rrently stored w ithin a page of the flash array mai n memory page program through buffer ( 8 2h, 8 5h) buffer w rite ( 8 4h, 8 7h) buffer to mai n memory page program ( 8 3h, 8 6h)
48 3597o?dflash?10/09 at45db321d 26. ordering information 26.1 ordering code detail at45d 32 ssu 1d? b atmel designator product family device density 32 = 32-megabit interface 1 = serial package option m = 8-pad, 6 x 5 x 1 mm mlf (vdfn) mw = 8-pad, 8 x 6 x 1 mm mlf (vdfn) s = 8-lead, 0.209" wide soic t = 28-lead, tsop device grade u = matte sn lead nish, industrial temperature range (-40c to +85c) device revision c = 24 ball bga
49 3597o?dflash?10/09 at45db321d notes: 1. the shipping carrier option is not marked on the devices. 2. standard parts are shipped with the page size set to 528 bytes. th e user is able to configure these parts to a 512-byte page size if desired. 3. parts ordered with suffix sl954 are shipped in bulk with the page size set to 512 bytes. parts will have a 954 or sl954 marked on them. 4. parts ordered with suffix sl955 are shipped in tape and reel with the page size set to 512 bytes. parts will have a 954 or sl954 marked on them. 26.2 green package options (pb/halide-fr ee/rohs compliant) ordering code (1)(2) package lead finish operating voltage f sck (mhz) operation range at45db321d-mu at45db321d-mu-sl954 (3) at45db321d-mu-sl955 (4) 8m1-a matte sn 2.7v to 3.6v 66 industrial (-40 c to 85 c) 2.7v to 3.6v at45db321d-mwu at45db321d-mwu-sl954 (3) at45db321d-mwu-sl955 (4) 8mw at45db321d-su at45db321d-su-sl954 (3) at45db321d-su-sl955 (4) 8s2 at45db321d-tu 28t AT45DB321D-CU 24c1 matte sn 2.7v to 3.6v 66 at45db321d-mu-2.5 8m1-a matte sn 2.5v to 3.6v 50 at45db321d-su-2.5 8s2 package type 8m1-a 8-pad, 6 x 5 x 1.0 mm, very thin micro lead-frame package mlf ? (vdfn) 8mw 8-pad, 8 x 6 x 1.0 mm, very thin micro lead-frame package mlf (vdfn) 8s2 8-lead, 0.209" wide, plastic gull wing small outline package (eiaj soic) 28t 28-lead, 8 mm x 13.4 mm, plastic thin small outline package, type i (tsop) 24c1 24-ball, 6mm x 8mm x 1,4mm ball grid array with a 1mm pitch 5 x 5 ball matrix
50 3597o?dflash?10/09 at45db321d 27. packaging information 27.1 8m1-a ? mlf (vdfn) title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 8 m1-a, 8 -p a d, 6 x 5 x 1.00 mm body, therm a lly enh a nced pl as tic very thin d ua l fl a t no le a d p a ck a ge (vdfn) d 8 m1-a ybr common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a ? 0. 8 5 1.00 a1 ? ? 0.05 a2 0.65 typ a 3 0.20 typ b 0. 3 5 0.40 0.4 8 d 5.90 6.00 6.10 d1 5.70 5.75 5. 8 0 d2 3 .20 3 .40 3 .60 e 4.90 5.00 5.10 e1 4.70 4.75 4. 8 0 e2 3 . 8 0 4.00 4.20 e 1.27 l 0.50 0.60 0.75 ? ? 12 o k 0.25 ? ? pin 1 id top view pin #1 notch (0.20 r) bottom view d2 e2 l b d1 d e1 e e a 3 a2 a1 a 0.0 8 c 0 s ide view 0 k 0.45 8 /2 8 /0 8
51 3597o?dflash?10/09 at45db321d 27.2 8mw ? mlf (vdfn) 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 mw, 8 -p a d, 8 x 6 x 1.0 mm body, very thin d ua l fl a t p a ck a ge no le a d (mlf) b 8 mw 5/25/06 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a ? ? 1.00 a1 ? ? 0.05 b 0. 3 5 0.40 0.4 8 d 7.90 8 .00 8 .10 d1 6. 3 0 6.40 6.50 e 5.90 6.00 6.10 e1 4.70 4. 8 0 4.90 e 1.27 l 0.45 0.50 0.55 k 0. 3 0 ref pin 1 id top view pin #1 id bottom view d1 e1 l b d e e a1 a s ide view k 1 pin #1 ch a mfer (c 0. 3 0) option a pin #1 notch (0.20 r) option b
52 3597o?dflash?10/09 at45db321d 27.3 8s2 ? eiaj soic title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 8s 2 s tn f 8s 2, 8 -le a d, 0.20 8? body, pl as tic s m a ll o u tline p a ck a ge (eiaj) 4/15/0 8 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to eiaj dr a wing edr-7 3 20 for a ddition a l inform a tion. 2. mi s m a tch of the u pper a nd lower die s a nd re s in bu rr s a ren't incl u ded. 3 . determine s the tr u e geometric po s ition. 4. v a l u e s b ,c a pply to pl a ted termin a l. the s t a nd a rd thickne ss of the pl a ting l a yer s h a ll me asu re b etween 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0. 3 5 0.4 8 4 c 0.15 0. 3 5 4 d 5.1 3 5. 3 5 e1 5.1 8 5.40 2 e 7.70 8 .26 l 0.51 0. 8 5 0 8 e 1.27 b s c 3 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d s ide view s i d e v i e w
53 3597o?dflash?10/09 at45db321d 27.4 28t ? tsop, type 1 2325 orchard park w ay san jose, ca 95131 title drawing no. r rev. 28t , 2 8 -lead ( 8 x 13.4 mm) plastic thin small o u tline package, type i (tsop) c 2 8 t 12/06/02 pi n 1 0o ~ 5o d1 d pin 1 identifier area b e e a a1 a2 c l gage pla n e seati n g pla n e l1 common dimensions (unit of meas u re = mm) symbol min nom max note n otes: 1. this package conforms to jedec reference mo-1 8 3. 2. dimensions d1 and e do not incl u de mold protr u sion. allo w a b le protr u sion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maxim u m. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.90 1.00 1.05 d 13.20 13.40 13.60 d1 11.70 11. 8 0 11.90 n ote 2 e 7.90 8 .00 8 .10 n ote 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.55 basic
54 3597o?dflash?10/09 at45db321d 27.5 24c1 - ball grid array 2325 orchard park w ay san jose, ca 95131 title drawing no. r rev. 24c1 , 24- b all (5 x 5 array), 6 x 8 x 1.4 mm body, 1.0 mm ball pitch chip-scale ball grid array package (cbga) a 24c1 04/11/01 dimensions in millimeters and (inches). controlling dimension: millimeters. a b c d e 54321 4.0 (0.157) 1.00 (0.039) ref 0.46 (0.01 8 ) dia ball typ 2.00 (0.079) ref 4.0 (0.157) 8 .10(0.319) 7.90(0.311) 1.40 (0.055) max 0.30 (0.012)mi n 6.10(0.240) 5.90(0.232) 1.00 (0.0394) bsc n o n -accumulati v e a1 id 1.00 (0.0394) bsc n o n -accumulati v e top view side view bottom view
55 3597o?dflash?10/09 at45db321d 28. revision history revision level ? release date history a ? november 2005 initial release b ? january 2006 added 6 x 5 mm mlf (vdfn) package. added text, in ?programming the configuration register?, to indicate that power cycling is re quired to switch to ?p ower of 2? page size after the opcode enable has been executed. corrected typographical error regarding the opcode for chip erase in ?program and erase commands? table. c ? march 2006 added preliminary. changed the sector size from 256k bytes to 64k bytes. added the ?legacy commands? table. d ? april 2006 added 8 x 6 mm mlf (vdfn) package. changed the sector size of 0a and 0b to 8 pages and 120 pages respectively. changed the product version code to 00001. e ? july 2006 corrected typographical errors. f ? august 2006 added errata regarding chip erase. added at45db321d-su to ordering information and corresponding 8s2 package. g ? september 2006 removed ?not recommended for new designs? note from ordering information for 8mw package. h ? february 2007 added at45db321d-cnu to ordering information and corresponding 8cn3 package. removed ?not recommended for new designs? comment from 8mw package drawing. i ? august 2007 added additional text to ?power of 2? binary page size option. changed t vscl from 50 s to 70 s. changed t rdpd from 30 s to 35 s. changed t xfr and t comp values from 400 s to 200 s. removed at45db321d-cnu from ordering information and corresponding 8cn3 package. j ? april 2008 added part number ordering code details for suffixes sl954/955. added ordering code details. k ? september 2008 corrected typographical errors in sector erase section. corrected a17+a16 from x (don?t care) to a for opcode 7ch in table 15-6. corrected pa8+pa7 from x (don?t care) to p for opcode 7ch in table 15-7. l ? february 2009 changed t dis (typ and max) to 27 ns and 35 ns, respectively.
56 3597o?dflash?10/09 at45db321d 29. errata 29.1 chip erase 29.1.1 issue in a certain percentage of units, the chip erase feature may not function correctly and may adversely affect device operation. therefore, it is recommended that the chip erase commands (opcodes c7h, 94h, 80h, and 9ah) not be used. 29.1.2 workaround use block erase (opcode 50h) as an alternative. the block erase function is not affected by the chip erase issue. 29.1.3 resolution the chip erase feature may be fixed with a new revision of the device. please contact atmel for the estimated availability of devices with the fix. m ? march 2009 changed deep power-down current values - increased typical value from 5 a to 15 a. - increased maximum value from 15 a to 25 a. n - april 2009 updated absolute maximum ratings added 24c1 24 ball bga package option deleted dataflash card package option o - october 2009 added the 2.5v v cc option removed at45db321d-mwu-2.5 and at45db321d-tu-2.5 from the ordering information table. revision level ? release date history
3597o?dflash?10/09 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support dataflash@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2009 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, everywhere you are ? , dataflash ? , rapids ? logo and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trade- marks of others.

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